Conventional LSI (Large Scale Integration) integrates elements in a two-dimensional plane on a silicon substrate. It is necessary to reduce the dimensions of one element (downscale) to increase the storage capacity in semiconductor memory devices (memory). However, in recent years, such downscaling has become difficult in regard to both technology and cost.
Although improvements to photolithography technology are necessary to downscale, current ArF immersion lithography has reached resolution limits at about the 40 nm rule; and it is necessary to introduce EUV (Extreme Ultra Violet) exposure apparatuses for further downscaling.
However, the introduction of EUV exposure apparatuses is not realistic due to extremely high costs. Moreover, even in the case where such downscaling could be achieved, unless the drive voltages and the like can be scaled, it is expected that physical limitations such as the breakdown voltage between elements will be reached.
Therefore, many ideas for three-dimensional memory have been proposed. However, because general three-dimensional memory devices require processes including at least three lithography processes for each layer, costs have not been reduced even with three dimensional structures; and stacking four or more layers may undesirably lead to higher costs.
The inventors of the application have proposed collectively patterned three-dimensionally stacked memory cells in consideration of such problems (for example, refer to JP-A 2007-320215 (Kokai)). According to such a method, it is possible to suppress cost increases because it is possible to form a stacked memory collectively regardless of the number of stacks.
Such three-dimensional collectively patterned memory capable of suppressing cost increases employs a MONOS (Metal Oxide Nitride Oxide Semiconductor) transistor as the memory cell.
Therefore, the proposed three-dimensional collectively patterned memory uses operations similar to those of conventional NAND flash memory. However, the memory cell portion employs not a structure having a floating gate but a so-called MONOS cell in which charge is programmed into a charge trap insulating film.
Further, due to the collective patterning processes, the MONOS insulating film is formed uniformly on the side wall of holes and is formed as a continuous film not only at the cell portions but also at inter-layer film portions between cells (hereinbelow also referred to as “between CG-CG”). Therefore, there is a risk of data retention deterioration due to the programmed charge moving due to effects from adjacent cells.
Such effects from adjacent cells have a relationship with the repeated programming and erasing of data. In other words, it is considered that a load accumulates in the MONOS insulating film between adjacent cells due to the repeated operations of programming and erasing data.